In most advanced integrated circuits, the embedded memory blocks amount to more than half of the total surface area of the circuit. In the future, it is expected that the memory blocks will exceed more than 70% of the total surface area of the circuit. The surface area of the memory cell therefore plays a vital role in the race towards miniaturization. For many years, the gain in integration density has been obtained by reducing the different dimensions of the transistors (the front end), the contacts (the middle end) and the metals (the back end), enabling the integration of ever-increasing numbers of memory cells on a given surface area of substrate.
The reduction of certain dimensions in the transistors has led to the appearance of parasitic physical effects which become non-negligible (in terms of variation of dopants, short channel effects, etc.) and affect miniaturization. Novel materials have therefore appeared along with novel transistor architectures in order to compensate for these parasitic effects.
However, the use of novel materials and/or novel architectures generally leads to difficulties of manufacture and/or problems of reliability of the integrated circuit. Similarly, the use of a novel type of transistor entails problems in terms of portability and compatibility of the already existing circuits as well as the circuit techniques used to improve performance.
Integrated circuits made with SOI technology have a certain number of advantages. Such circuits generally show lower static and dynamic electricity consumption for equivalent performance, owing to better electrostatic control of the channel by the gate. Because there is a non-doped channel, the dispersions of the electrical characteristics are also smaller. Such circuits generally result in lower parasitic capacitances, thus improving switching speed. Furthermore, the latch-up or parasitic triggering phenomenon encountered by CMOS transistors in bulk technology can be avoided to the benefit of operating robustness, owing to the presence of the insulating oxide layer. Such circuits therefore prove to be particularly suited to SoC type applications. It is generally noted that SOI integrated circuits are less sensitive to the effects of ionizing radiation and hence prove to be more reliable in applications where such radiation can give rise to operational problems, especially in space applications. SOI integrated circuits can especially include SRAM random-access memories or logic gates. The making of SOI integrated circuits also remains relatively similar to that of bulk technology.
Reducing the static consumption of logic gates while at the same time increasing their switchover speed has been the subject of much research. Certain integrated circuits being developed integrate both low-consumption logic gates and high-switching-speed logic gates. To generate both these types of logic gates on a same integrated circuit, fast-access logic gates or low-consumption logic gates are chosen from libraries of logic gates. In bulk technology, the threshold voltage level of transistors of a same type is modulated by differentiating their channel doping level. However, in FDSOI (Fully Depleted Silicon-On-Insulator) technology, the doping of the channel is almost zero. Thus, the channel doping level in the transistors cannot show major variations without losing the associated advantages, and this fact makes it impossible to differentiate the threshold voltages by bringing this doping into play. The threshold voltages in non-doped channel FDSOI technology are thus essentially determined by the work function of the gate. For nMOS transistors, a work function slightly below the midgap, known as an N-type work function, is generally desired to obtain threshold voltages between 0.2 and 0.5V. Symmetrically, for pMOS transistors, a work function slightly above the midgap, called a P-type work function, is generally desired to obtain threshold voltages between −0.2 and −0.5V.
In order to have distinct threshold voltages for different FDSOI technology transistors, there are also known ways of using a biased ground plane placed between an insulating thin-oxide layer and the silicon substrate. By playing on the doping of the ground planes and on their biasing, it is possible to define a range of threshold voltages for the different transistors. We could thus have low-voltage-threshold or LVT transistors, high-voltage-threshold or HVT transistors and medium or standard-voltage-threshold or SVT transistors.
For certain functions of the circuit, it is possible to combine transistors of a same type, for example LVT or HVT transistors, in a same region. However, certain functions of the circuit require the contiguous joining of different types of transistors with ground planes having different biases. The designing of such functions of the circuit proves to be relatively difficult because additional designing constraints have to be taken into account. FIGS. 1a to 1c provide an example of pairs of nMOS and pMOS transistors of different types, namely HVT, SVT and LVT types respectively.
FIG. 1a shows an example of a pair of HVT-type transistors, namely an nMOS transistor 1nH and a pMOS transistor 1pH. The transistors 1nH and 1pH are made with SOI technology. The transistors 1nH and 1pH are made on a layer of silicon substrate 101H. The transistors 1nH and 1pH comprise respective buried insulating layers, 103nH and 103pH, separated from the substrate layer 101H by means of respective ground planes 102nH and 102pH and wells 112nH and 112pH. The insulating layers 103nH and 103pH are surmounted by an active silicon layer. The active silicon layer of the transistor 1nH comprises a source, a channel 104nH and a drain. The active silicon layer of the transistor 1pH comprises a source, a channel 104pH and a drain. The ground planes 102nH and 102pH enable the electrostatic control of the transistor to be improved by limiting the penetration of the electrical fields generated by the drain and the source beneath the channel 104nH and 104pH. The reduction of the lateral electrostatic coupling reduces short-channel effects and limits the drain-induced depletion effect through DIBL. The channels 104nH and 104pH are lined respectively with gate oxide layers 105nH and 105pH. The gate oxides 105nH and 105pH are surmounted by respective gate stacks comprising metal layers 108nH and 108pH and polysilicon layers 111nh and 111ph. The stacks are demarcated laterally by spacers 110nH and 110pH. Insulation trenches 106H, 107H and 109H are placed around the transistors 1nH and 1pH.
To obtain HVT type transistors, the ground plane 102nH has P-type doping and is biased to ground, and the ground plane 102pH has an N-type doping and is biased to Vdd, and thin BOX insulating layers 103nH and 103pH, (with a typical thickness of 10 to 50 nm) are used. The ground plane 102nH could also be biased to a voltage ranging from Gnds (Gnds being a voltage below ground voltage Gnd) and Vdd/2. The ground plane 102pH could also be biased to a voltage ranging from Vdd/2 (Vdd being a high-level voltage) to VddH (VddH>Vdd). The wells 112nH and 112pH have respective P-type and N-type dopings. The ground planes 102nH and 102pH are biased by means of wells 112nH and 112pH respectively.
FIG. 1b shows an example of a pair of SVT-type transistors, namely an nMOS transistor 1nS and a pMOS transistor 1pS. The transistors 1nS and 1pS have substantially the same structure as the transistors 1nH and 1pH: they are made on a silicon substrate layer 101S comprising respective buried insulating layers 103nS and 103pS separated from the substrate layer 101S by means of the respective ground planes 102nS and 102pS and wells 112nS and 112pS. The insulating layers 103nS and 103pS are surmounted by an active silicon layer. The active silicon layer of the transistor 1nS has a source, a channel 104nS and a drain. The active silicon layer of the transistor 1pS has a source, a channel 104pS and a drain. The channels 104nS and 104pS are lined respectively by gate oxide layers 105nS and 105pS. The gate oxide layers 105nS and 105pS are surmounted by respective gate stacks comprising metal layers 108nS and 108pS and polysilicon layers 111nS and 111pS. The stacks are demarcated laterally by spacers 110nS and 110pS. Insulating trenches 106S, 107S and 109S are placed around the transistors 1nS and 1pS.
To obtain SVT type transistors, the ground plane 102nS has an N-type doping and is biased to ground and the ground plane 102pS has P-type doping and is biased to Vdd, and thin insulating BOX layers 103nS and 103pS are used. The ground plane 102nS could also be biased to a voltage ranging from Gnds (with Gnds<Gnd) and Vdd/2. The ground plane 102pS could also be biased to a voltage of Vdd/2 to VddH. The wells 112nS and 112pS have respective P-type and N-type dopings. The biasing of the ground planes 102nS and 102pS is done by means of the wells 112nS and 112pS respectively.
FIG. 1c shows an example of a pair of LVT-type transistors comprising an nMOS transistor 1nL and a pMOS transistor 1pL. The transistors 1nL and 1pL have substantially the same structure as the transistors 1nH and 1pH: they are made on a silicon substrate layer 101L comprising respective buried insulating layers 103nL and 103pL separated from the substrate layer 101H by means of respective ground planes 102nL and 102pL and wells 112nL and 112pL. The insulating layers 103nL and 103pL are surmounted by an active silicon layer. The active silicon layer of the transistor 1nL has a source, a channel 104nL and a drain. The active silicon layer of the transistor 1pL has a source, a channel 104pL and a drain. The channels 104nL and 104pL are lined respectively with gate oxide layers 105nL and 105pL. The gate oxides 105nL and 105pL are surmounted by respective gate stacks comprising metal layers 108nL and 108pL and polysilicon layers 111nL and 111pL. The stacks are demarcated laterally by spacers 110nL and 110pL. Insulating trenches 106L, 107L and 109L are placed around the transistors 1nL and 1pL.
To obtain LVT type transistors, the ground plane 102nL has an N-type doping and is biased to Vdd and the ground plane 102pL has P-type doping and is biased to ground, and thin insulating BOX layers 103nL and 103pL are used. The ground plane 102nH could also be biased to a voltage of Vdd/2 to VddH. The ground plane 102pH could also be biased to a voltage of Gnds to Vdd/2. The wells 112nL and 112pL have respective N-type and P-type dopings. The ground planes 102nL and 102pL are biased by means of the wells 112nL and 112pL respectively.
It is also possible to integrate different gate materials for these transistors to modify the threshold voltages of the different transistors. To this end, it is possible to use different types of doping in the polysilicon layers, make different types of polysilicon layers or use different materials in the metal layers so as to obtain gates with distinct work functions.
These technical solutions provide for a specialization of the transistors in the logic gates and the memory cells of the integrated circuit. The characteristics of the integrated circuits designed may thus be more specifically defined.
The process of implanting dopants in the structure leads to undesirable variations in concentration at the edge of the implantations, inducing undesirable doping of the channel of the transistors. At the scale of the integrated circuits used, these variations take the form of effects known as WPE (well proximity effects) that are not negligible and affect the reliability and efficiency of manufacture of such circuits. The use of different gate materials also has non-negligible consequences on the complexity of the manufacturing process and its efficiency, especially as the integrated circuit has high density.